1. Field of the Invention
The present invention pertains to etching trenches in silicon substrates and cleaning processes to remove deposits from reactors used in etching processes. The method of the invention is generally applicable to the etching of silicon, but is particularly useful in the etching of deep trenches. Silicon deep trench etching is most commonly used in capacitor technology, in particular, in DRAM applications. Other applications for the present etching method include the etching of shallow trenches used in applications such as device isolation; the etching of polysilicon gates; and the etching of silicide layers. In addition, the present etching method is useful in process sequences utilized in the micro machining of silicon surfaces for biomedical applications, for example.
2. Description of the Related Art
Although the silicon etching method of the present invention is useful in a number of applications, as mentioned above, one of the most important applications is the etching of high aspect ratio (over about 20:1) trench capacitors used in DRAM applications. The profile of the etched trench must meet strictly defined industry standards. The current specification for a 256 Mb DRAM capacitor having a critical diameter ranging from about 0.15 to about 0.38 .mu.m calls for strict profile taper control.
The development of manufacturing technology for fabrication of the trench structure 103 shown in FIG. 1C (and for silicon trench structures of the future) depends on development of a plasma etch technology which provides adequate selectivity for the silicon substrate over the patterning layer 108, the masking layer 106, and the dielectric layer 104, while providing an economically feasible etch rate for the silicon substrate layer 102, and enabling the necessary profile control as the dimensions of trench 103 are reduced. Additionally, as new profile control processes are developed, production worthy chamber cleaning methods and chemistries must also be developed to ensure economically feasible substrate throughput.
The typical approach to forming deep trenches in a representative DRAM stack (e.g., the DRAM stack 100 illustrated in FIG. 1A) is conducted in a linear fashion, first etch a via through the stack 100 to the substrate surface 105 or a substrate open step, then etch the trench 103. This division of the trench process led to process sequences intended to optimize processing in each of these two divisions-substrate open and trench etch.
FIG. 1A illustrates a portion of a representative structure 100 useful in capacitor fabrication. Structure 100 includes a silicon substrate 102, a dielectric pad oxide layer 104, a masking layer or hard mask 106, and a patterning layer 108. Typically the dielectric pad oxide layer is silicon dioxide, the masking layer is silicon nitride, and the patterning layer material is borosilicate glass (BSG) or a silicon oxide deposited using tetraethyl orthosilicate (TEOS), or a combination thereof. In some applications, a dielectric Anti-Reflective Compound (ARC) layer such as siliconoxynitride may be used in combination with the patterning layer.
Generally, trench formation production processes are accomplished by having a chamber dedicated to the substrate open process and another chamber dedicated to the trench etch process. The number of chambers used for each process depends upon throughput considerations such as the relative duration of the etch processing cycles and cleaning cycles as well as the specific dimension of the trench being formed and the thickness of the individual layers of structure 100.
A representative deep trench etch process will be described in relation to a structure 100 where the thickness of the borosilicate glass patterning mask 108 is about 7,000 .ANG.; the thickness of silicon nitride masking layer 106 is about 2,200 .ANG.; the thickness of pad oxide dielectric layer 104 is about 80 .ANG.. FIGS. 1A, 1B and 1C are not to scale. FIG. 1A illustrates a substrate having stack 100 as it is loaded into the first processing chamber.
In the first processing chamber, which may be for example, a Magnetically Enhanced Reactive Ion Etch (MERIE) Chamber, or other processing chamber suitable for conducting the substrate open process. Reactive gases are introduced and a plasma is formed to expose the substrate 102 top surface 105 by removing patterning layer 1Z08, masking layer 106 and pad oxide layer 104. The mask is typically opened by plasma etch using CHF.sub.3 and O.sub.2 based chemistry. Typical etch rates for this type of process are about 1 .mu.m/minute. Periodic dry cleaning is conducted after processing about 100 wafers. In this example, about 9280 .ANG. of material is removed during the substrate open process.
During the etching processes, etchant residue (often referred to as a polymer) deposits on the walls and other component surfaces inside the etching chamber. The composition of the etchant residue depends upon the chemical composition of vaporized species of etchant gas, the material being etched, and the mask layer on the substrate. The vaporized and gaseous species condense to form etchant residue comprising polymeric byproducts composed of hydrocarbon species from the resist; gaseous elements such as fluorine, chlorine, oxygen, or nitrogen; and elemental silicon or metal species depending on the composition of the material being etched. The polymeric byproducts deposit as thin layers of etchant residue on the walls and components in the chamber. The composition of the etchant residue typically varies considerably across the chamber surface depending upon the composition of the localized gaseous environment, the location of gas inlet and exhaust ports, and the geometry of the chamber. The compositionally variant, non-homogeneous, etchant residue formed on the etching chamber surfaces has to be periodically cleaned to prevent contamination of the substrate.
Typically, after processing the substrate open process on about 100 wafers, an in-situ plasma "dry-clean" process is performed in an empty etching chamber to clean the chamber. Periodically, the chamber is taken out of service to conduct a wet clean to more completely remove processing residue.
After conducting the substrate open process, the substrate is transferred into the second processing chamber to conduct the trench etch process. The second processing chamber may be any processing chamber suitable for etching deep trenches in substrates such as, for example, a Decoupled Plasma Etch Reactor as manufactured by Applied Materials, Inc. of Santa Clara Calif. During the trench etch process, a mixture of processes gases is introduced into the chamber and formed into a plasma which is used to remove substrate material to form the trench. A typical deep trench structure 103 is illustrated in FIG. 1C. The top portion 110 of the trench 103, which extends from the silicon surface 105 into the silicon substrate 102 a depth 114 of about 1.5 .mu.m is specified to taper at an angle of 88.5.degree.+/-0.5.degree.. The bottom portion 112 of the trench 103, which extends beneath the top portion 110 for an additional depth 116 of about 6.5 .mu.m is specified to taper at an angle of 89.5.degree.+/-0.50.degree.. The bottom of the trench is illustrated as rounded but may be bottle shaped rather than tapered.
Related U.S. patent application, Ser. No. 09/102,527, filed Jun. 22, 1998, assigned to the assignee of the present invention, describes a method for etching high aspect ratio trenches in silicon where at least a portion of the silicon trench, particularly toward the bottom of the trench, is etched using a combination of reactive gases including fluorine-containing compound which does not contain silicon (FC); a silicon-containing compound (SC), which preferably also contains fluorine; and oxygen (O.sub.2). The use of a fluorine-containing silicon compound is preferred as a means of improving the etch rate and removing debris from the etched surfaces, while providing supplemental silicon availability for protection (passivation) of the etched mask sidewall and the upper etched portion of the trench, during etching of the bottom portion of the trench. The non-fluorine-containing source of silicon is preferred when the desired trench profile requires additional protection of the etched mask sidewall and the etched surface at the top of the trench during etching the bottom portion of the trench.
The trench etch process may take as long as ten minutes to complete. While the combined fluorine containing gas, silicon containing gas, and oxygen plasma provides superior profile control for deep trenches, the process creates deposits within the processing reactor. The degree of deposit accumulation is such that the reactor typically requires cleaning after each substrate is processed. This cleaning process is conducted with a dummy substrate in the chamber and requires about 120 seconds to complete. As a result, the typical cycle time to etch a trench in a substrate is about one minute for substrate open process; about 10 minutes for trench formation, and about 2 minutes to clean the chamber after the trench etch.
Deposit accumulation during the trench etch process may be reduced by the introduction of cleaning gas into the plasma mixture (i.e. a self clean chemistry) or, as disclosed in U.S. patent application Ser. No. 09/102,527, SiF.sub.4 may be turned off during the last 90 seconds of the trench process. However, these methods of deposit reduction may have adverse impacts on the trench process. The addition of self-clean chemistry, while reducing accumulations, increases the number of process gases required to control and introduces complexities in the interactions between the various trench etch gases and the self-clean gases. Turning off SiF.sub.4 during the last 90 seconds of the trench etch may also negatively impact the hard mask layer since the SiF.sub.4 reduces lateral erosion. As decreased device size leads to deeper trenches, the longer trench etch times needed for these deeper trenches increases the risk of lateral erosion. Thus, the reduced silicon gas species supplied to the chamber reduces accumulations at the possible expense of lateral mask erosion.
Thus, what is needed is a method of etching trenches in silicon substrates, particularly in the formation of deep trenches, that overcomes the shortcoming of the prior art and provides increased throughput.